# 902 Signal Integrity Engineer

Email:	kreed@tkophoenix.com
Posting Date:	2/1/09
Location:	Silicon Valley

Client Company is a start-up firm designing 25 and 40 Gigabyte SERDES chips that target video applications for telecom equipment.  Company is presently pre-VC stage and looking for one or two key contributors to join start-up team.

Report to: Chief Technology Officer

Overview of Position: Key engineering position with product definition and design responsibilities. Team collaboration is critical.

RESPONSIBILITY

• Participate in product definition
• SERDES board design

QUALIFICATIONS:

• BS Electrical Engineering
• Minimum of 2 years experience in circuit design of high frequency PLL and I/O design
• Knowledge of full custom layout, signal integrity analysis & spice simulators is highly desirable.
• Experience with 10 Gigabyte SERDES board design

COMPENSATION

Equity in start-up company and, as available, market-rate compensation