# 906 Principal Mixed Signal Engineer

Email:	kreed@tkophoenix.com
Posting Date:	8/15/09
Location:	Silicon Valley

Client Company is a start-up firm designing very high speed SerDes chips that will enable the next generation of the network.  Company is presently pre-VC stage and looking for one or two key contributors to join start-up team.

Report to: Chief Technology Officer
Title of Position:  Principal Mixed-Signal Engineer

Overview of Position: 

Key engineering position for defining and designing high-performance SerDes parts.  Work with a team of digital designers, signal integrity expert, application and product engineers to design next-generation networking products. 
Responsibilities:

1. Define architecture and circuit implementations for high-performance low-power Serdes IPs in standard CMOS processes.
2. Develop a flexible top-down design modeling and verification process that models the system accurately from concept through design and verification.
3. Specifications and design implementations of mixed-signal circuit blocks related to Serdes IPs.
4. Report the results of IC design, analysis and evaluation.
5. Layout supervision of floor-planning and circuit blocks including the entire chip is key.
6. Post-silicon validation using lab equipment.
7. Interfacing with application/marketing team, customers and vendors to understand specific product requirements.

Qualifications:

1. MS/PhD with 8 years of related experience.
2. A proven track record of delivering high-speed Serdes ASSPs/ASICs into volume production in standard CMOS processes- CEI6G, CEI11G, HDMI, XAUI, PCIE, 10G Ethernet and SONET applications.
3. Minimum of five years extensive experience in designing some of the critical blocks for SerDes IPs- equalizers including FFEs and DFEs, PLLs, CDRs, VCOs, serializers and de-serializers is a must.
4. Experience in implementing supply-regulated techniques for Serdes building blocks is a plus.
5. Extensive knowledge of process technology including device modeling and noise theory, and physics related to sub-micron CMOS processes is a must.
6. Extensive experience with simulation tools (Cadence, Spectre/Smartspice etc.) is required.
7. Experience in characterizing high-speed SerDes in the laboratory is a must.
8. Self motivated, team player with strong communication skills and ability to work with aggressive schedules is essential.

Compensation:

Equity in start-up company and, as available, market-rate compensation