# 907 Principal Logic Design Engineer

Email:	kreed@tkophoenix.com
Posting Date:	8/15/09
Location:	Silicon Valley

Client Company is a start-up firm designing very high speed SerDes chips that will enable the next generation of the network.  Company is presently pre-VC stage and looking for one or two key contributors to join start-up team.

Report to: Chief Technology Officer
Title of Position: Principal Logic Design Engineer

Overview of Position

Provide technical leadership and guide the successful completion of all phases of high-speed digital circuit design. Participate in the definition of chip and system interconnects. Work with a team of I/O designers, digital designers, signal integrity expert, application and product engineers to design next-generation networking products. 
Responsibilities:

1. Must apply advanced technical principles, theories and concepts and develop appropriate solutions for integrating complex Serdes IPs in ASSPs for achieving throughputs beyond 10Gbps in standard CMOS processes.
2. Establish solid design process, design review and verification flow for the digital/mixed-signal team.
3. Architecture definition of digital modules as well as analysis of their interfaces with other digital/analog circuits.
4. Develop a test strategy for evaluating SerDes as well as all digital blocks for both prototype testing and final production test.
5. Design and implementation of digital algorithms that calibrate analog circuits.
6. Develop innovative techniques to minimize overall power dissipation and mitigate EMI issues.
7. Post-silicon validation using lab equipment.
8. Interfacing with application/marketing team, customers and vendors to understand specific product requirements.

Qualifications:

1. MS/PhD with 8 years of related experience.
2. A proven track record of driving an engineering team to deliver some of the high-speed SerDes ASSPs into volume production in standard CMOS processes- CEI6G, CEI11G, HDMI, XAUI, PCIE, 10G Ethernet and SONET applications.
3. Minimum of five years experience in the design of high-speed data paths.
4. Experience in designing on-chip test methodology for Ethernet parts.
5. Experience with implementing FEC and PCS digital blocks for any of the IEEE802.3 standards is a must.
6. Extensive knowledge of hardware description languages like verilog HDL and experience in behavioral and RTL coding.
7. Candidates should have extensive experience from past projects including good knowledge of logic synthesis and timing analysis.
8. Knowledge of physical design and verification: layout, place and route, and verification. Knowledge of P&R at block and module level and familiar with design flow and strategy.
9. Extensive knowledge in memory and communication peripherals (e.g. USB, SATA, Flash, DDR) is a plus.
10. Proficiency in FPGA design, micro-controller architecture for Ethernet applications is a plus.
11. Experience in working with state-of-the art CMOS processes is a plus.
12. Self motivated, team player with strong communication skills and ability to work with aggressive schedules is essential.

Compensation:

Equity in start-up company and, as available, market-rate compensation