# 915 Mixed Signal/PLL Frequency Synthesizers
Client Company is a start-up firm designing very high speed SerDes chips that will enable the next generation of the network. Company is presently pre-VC stage and looking for one or two key contributors to join start-up team.
Report to: Chief Technology Officer
Overview of Position: Key engineering position for defining and designing high-performance PLLs/frequency synthesizers. Work with a team of mixed-signal designers, digital designers, signal integrity expert, application and product engineers to design next-generation networking products.
Responsibilities:
- Define architecture and circuit implementations for high-performance low-power PLLs/Frequency-Synthesizers in standard CMOS processes.
- Develop a flexible top-down design modeling and verification process that models the PLL block accurately from concept through design and verification.
- Specifications and integration of PLLs with other building blocks and co-verification.
- Develop state-of-the-art clock distribution strategies at the chip-level.
- Report the results of IC design, analysis and evaluation.
- Layout supervision of floor-planning and circuit blocks in relation to the top chip level is the key.
- Post-silicon validation using lab equipment.
- Interfacing with application/marketing team, customers and vendors to understand specific product requirements.
Qualifications:
- MS/PhD with 8 years of related experience.
- A proven track record of delivering high-speed PLLs for RF and Serdes applications into volume production in standard CMOS processes- 802.11a and 802.11b based RF transceivers, CEI6G, CEI11G, HDMI, XAUI, PCIE, 10G Ethernet and SONET applications.
- Experience in implementing supply-regulated techniques for PLLs is a must.
- Extensive knowledge of process technology including device modeling and noise theory, and physics related to sub-micron CMOS processes is a must.
- Extensive experience with simulation tools (Cadence, Spectre/Smartspice etc.) is required.
- Experience in characterizing high-performance PLLs in the laboratory is a must.
- Self motivated, team player with strong communication skills and ability to work with aggressive schedules is essential.
Compensation:
Equity in start-up company and, as available, market-rate compensation
